Why does my Intel® Stratix® 10 PCIe* IP fail to perform a directed Gen3 or Gen2 speed change or a change to the L1 state?

Due to a problem with the Intel® Stratix® 10 PCIe* Hard IP, it will not perform a directed speed change if an Electrical Idle Ordered Set (EIOS) is never received or is corrupted. It may also fail to change to the L1 state. The following speed or state changes are affected:

1. Gen3 to Gen2
2. Gen2 to Gen3
3. Gen3 L0 to L1 state
4. Gen2 L0 to L1 state

Note: The Intel® Stratix® 10 PCIe* Hard IP does not support power savings in the L1 state.

This problem does not affect initial link up.

This problem affects Intel® Stratix® 10 GX L-Tile ES3 or L-Tile Production devices, all Intel® Stratix® 10 SX L-Tile devices (ES1 and Production), and Intel® Stratix® 10 GX H-Tile ES2 devices.

Intel® Stratix® 10 GX H-Tile Production devices are not affected.