Device Family: Intel® Stratix® 10

Type: Answers, How-To

Area: Intellectual Property

Last Modified: February 26, 2018
Version Found: v17.1
Bug ID: FB: 537224;
IP: Avalon-ST Stratix 10 Hard IP for PCI Express

Why does Intel® Stratix® 10 PCIe* Hard IP with SR-IOV drop outstanding completion TLPs of different PFs that use the same tag value?


Due to a problem with the Intel® Stratix® 10 PCIe* Hard IP with SR-IOV that improperly tracks tag value across physical functions (PFs), the Hard IP drops subsequent completion TLPs for a different PF that has the same tag value if that particular tag value is being actively tracked for another PF's non-posted request.


To work around this problem, use unique tag value for outstanding non-posted requests from different PFs.

This limitation and workaround will be documented in a future version of the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCIe* Solutions User Guide.