Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property

Why does the Intel® Stratix® 10 PCIe* IP core infer a latch when used in root port mode?


When using the Intel® Stratix® 10 PCIe* IP core in root port mode, the following inferred latch warning will be reported during analysis and synthesis:

Warning (13228): Verilog HDL or VHDL warning at latch inferred for net eop_cycles[3]

This problem has been confirmed as a bug.


No workaround for this problem exists.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.