Device Family: Intel® Arria® 10, Arria® V, Stratix® V

Type: Answers, Errata

Area: Intellectual Property

Last Modified: January 17, 2018
Version Found: v16.0
Version Fixed: v17.1
Bug ID: FB: 527473;

Why is the Intel® HDMI* IP RX vid_lock signal deasserted when the video timing geometry is inconsistent?


Due to a problem with the Intel® HDMI* IP, the signal RX vid_lock may not assert if video timing geometry is inconsistent.

The HDMI RX IP checks for consistent HSYNC width, VSYNC width, Htotal, Hactive, Vtotal, and Vactive parameters across frames to qualify stable video and assert vid_lock.

If these video parameters are inconsistent across frames vid_lock is deasserted and vid_data, vid_hsync, vid_vsync, and vid_de are invalid.


This problem is fixed in version 17.1 of the Intel® Quartus® Prime software.