Article ID: 000082529 Content Type: Troubleshooting Last Reviewed: 01/17/2018

Why is the Intel® HDMI* IP RX vid_lock signal deasserted when the video timing geometry is inconsistent?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Intel® HDMI* IP, the signal RX vid_lock may not assert if video timing geometry is inconsistent.

    The HDMI RX IP checks for consistent HSYNC width, VSYNC width, Htotal, Hactive, Vtotal, and Vactive parameters across frames to qualify stable video and assert vid_lock.

    If these video parameters are inconsistent across frames vid_lock is deasserted and vid_data, vid_hsync, vid_vsync, and vid_de are invalid.

    Resolution

    This problem is fixed in version 17.1 of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs