Device Family: Intel® Arria® 10, Arria® V, Cyclone® V, Stratix® V

Type: Answers, Errata

Area: Intellectual Property


Last Modified: January 12, 2018
Version Found: v13.1
Version Fixed: v17.0
Bug ID: FB: 406585;
IP: DisplayPort

Why does the Intel® DisplayPort IP have no audio transport for small horizontal blanking periods?

Description

Due to a problem with the DisplayPort IP, the DisplayPort TX core is not able to transport any audio sample when the resolution of horizontal blanking is smaller than the period shown below.

  • For quad symbol mode (SYMBOLS_PER_CLOCK = 4)
    • The minimum horizontal blanking period (in link clock cycles) to transport audio is 22, 21, 20 for transceiver lanes 1, 2, and 4, respectively. 
  • For dual symbol mode (SYMBOLS_PER_CLOCK = 2)
    • The minimum horizontal blanking period (in link clock cycles) to transport audio is 38, 35, 34 for transceiver lanes 1, 2, and 4, respectively. 

Workaround/Fix

This problem is fixed in version 17.0 of the Intel® Quartus® Prime software.