Device Family: Intel® Arria® 10

Type: Answers

Area: Intellectual Property

Last Modified: June 11, 2018

Version Found: v17.1

Bug ID: FB: 557754;

IP: 10GBASE-R PHY Intel FPGA IP, 1G 10GbE and 10GBASE-KR PHY Intel Arria 10 FPGA IP

Why do the Intel® Arria® 10 10GBASE-R Design Example User Guide and simulation test bench file show an incorrect Tx/Rx SC FIFO offset address ?

Description

Due to a problem with the Intel® Arria® 10 10GBASE-R design example, register map offset address for RX SC FIFO is 9400h and TX SC FIFO is 9600h.

However in the "Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide" (ug-20016), offset address for RX SC FIFO is D400h and TX SC FIFO is D600h.

Workaround/Fix

This problem will be fixed in a future version of the Intel® Quartus® Prime software.

The 10GBASE-R design example's register map offset address for TX SC FIFO and RX SC FIFO will be amended to match with register map offset address in ug-20016 design example user guide.

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