Due to a problem with the Intel® Arria® 10 10GBASE-R design example, register map offset address for RX SC FIFO is 9400h and TX SC FIFO is 9600h.
However in the "Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide" (ug-20016), offset address for RX SC FIFO is D400h and TX SC FIFO is D600h.