Device Family: Intel® Stratix® 10

Type: Errata

Area: Intellectual Property


Last Modified: May 29, 2018
Version Found: v18.0
Bug ID: FB: 553937;

Why does 25G Ethernet IP's dynamic generated example design fail timing in Stratix 10 ES1 and ES2 devices?

Description

Due to a problem in Intel® Quartus® Prime Pro version 18.0, the 25G Ethernet IP's dynamic generated example design may fail timing closure.

The affected variants are as below:

  • 25G with IEEE 1588 Example Design
  • 10G/25G with IEEE 1588 Example Design
  • 25G with IEEE 1588 Example Design and RSFEC
  • 10G/25G with IEEE 1588 Example Design and RSFEC

Workaround/Fix

Launch Design Space Explorer II and perform seed sweep to get best quality of fitter placement as Stratix® 10 FPGA timing model is still at preliminary stage pending engineering characterization.