Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers

Area: Intellectual Property


Last Modified: October 24, 2018
Version Found: v18.1
Bug ID: FB: 604183;

Why do the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the .pin file?

Description

Due to a problem in the Intel® Quartus® Prime software version 18.1 and earlier, the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP do not appear in the Quartus .pin file.

Workaround/Fix

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.