Why do I see marginal hold time failures when compiling the JESD204B IP targeting Intel® Stratix® 10 L-tile production devices?

Due to different placement and fitting of the JESD204B IP compiled across different seeds in the Intel® Quartus® Prime Pro software, you may see marginal hold time failures for interfaces with data rates rates at 13.5Gbps and 15Gbps or above. You may see this problem when targetting Intel Stratix® 10 L-tile production devices with a core speed grade of -2 or -1.