Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: May 10, 2018
Version Found: v17.1
Bug ID: FB: 555465;

Why do I see hold time violations in the Low Latency 40G Ethernet Intel® FPGA IP core, when KR4 is enabled?

Description

Due to a problem with the Low Latency 40G Ethernet Intel® FPGA IP core on Intel® Stratix® 10, you may see minor hold time violations when the KR4 feature is enabled. 

Workaround/Fix

A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.