Device Family: Intel® Arria® 10, Arria® V, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Stratix® V

Intel Software: Quartus II, Quartus Prime Standard

Type: Answers, Errata

Area: Intellectual Property


Last Modified: April 10, 2018
Version Found: v14.0
Bug ID: FB: 445621;
IP: JESD204B

Why do I observe intermittent error assertion when performing multiple resets of the JESD204B IP RTL state machine control example design?

Description

When performing multiple resets of the JESD204B IP RTL state machine control Example Design implemented in Intel® Arria® 10, Stratix® V, Arria V or Cyclone® V devices, you may observe interrupt pin(s) (jesd204_tx_int, and/or jesd204_rx_int) being asserted due to error(s), which can be read from the tx_err (0x60), rx_err0 (0x60) and rx_err1 (0x64) registers.

Workaround/Fix

For Arria 10 devices, use the NIOS II processor design example instead.

For Stratix V, Arria V or Cyclone V devices, perform the following modifications to the RTL :

(1) Modify top level module jesd204b_ed in jesd204b_ed.sv file.

Define active high reset wires:

   wire              tx_link_rst_sync;

   wire              tx_frame_rst_sync;

   wire              rx_link_rst_sync;

   wire              rx_frame_rst_sync;

   wire              global_rst_sync;

 

Modify the polarity of reset in the wire assignments below:

   // Hold core in reset mode until transceiver is ready

   assign global_rst_n_sync = ~global_rst_sync; // Add global_rst_n_sync assignment

   assign tx_avs_rst_n   = avs_rst_n;

   assign rx_avs_rst_n   = avs_rst_n;

   assign tx_frame_rst_n = ~tx_frame_rst_sync;

   assign rx_frame_rst_n = ~rx_frame_rst_sync;

   assign tx_link_rst_n  = ~tx_link_rst_sync;

   assign rx_link_rst_n  = ~rx_link_rst_sync;

 

altera_reset_controller is an active high reset synchronizer. Modify the input and output of the reset synchronizer instantiations accordingly to reflect the correct polarity:

   //    

   // Reset synchronizers for global reset (mgmt clock domain)  

   //  

   altera_reset_controller #(

      .NUM_RESET_INPUTS        (1),

      .OUTPUT_RESET_SYNC_EDGES ("deassert"),

      .SYNC_DEPTH              (2)

   ) u_avs_rst_sync (

      .reset_in0  (~global_rst_n), 

      .clk        (mgmt_clk),                                

      .reset_out  (global_rst_sync)

   );

 

Perform bitwise AND on wire_tx_ready & wire_rx_ready which are bus signals.

   //   

 

   // Reset synchronizers for transport layer reset (frame clock domain)

   //   

   altera_reset_controller #(

      .NUM_RESET_INPUTS        (1),

      .OUTPUT_RESET_SYNC_EDGES ("deassert"),

      .SYNC_DEPTH              (2)

   ) u_tx_frame_rst_sync (

      .reset_in0  (~(wire_frame_rst_n & &wire_tx_ready)), 

      .clk        (frame_clk),                                

      .reset_out  (tx_frame_rst_n_sync)

   );

 

   altera_reset_controller #(

      .NUM_RESET_INPUTS        (1),

      .OUTPUT_RESET_SYNC_EDGES ("deassert"),

      .SYNC_DEPTH              (2)

   ) u_rx_frame_rst_sync (

      .reset_in0  (~(wire_frame_rst_n & &wire_rx_ready)), 

      .clk        (frame_clk),                                

      .reset_out  (rx_frame_rst_n_sync)

   );

 

   //    

   // Reset synchronizers for base core reset (link clock domain)

   //  

   altera_reset_controller #(

      .NUM_RESET_INPUTS        (1),

      .OUTPUT_RESET_SYNC_EDGES ("deassert"),

      .SYNC_DEPTH              (2)

   ) u_tx_link_rst_sync (

      .reset_in0  (~(wire_link_rst_n & &wire_tx_ready)), 

      .clk        (link_clk),                                

      .reset_out  (tx_link_rst_n_sync)

   );

   

   altera_reset_controller #(

      .NUM_RESET_INPUTS        (1),

      .OUTPUT_RESET_SYNC_EDGES ("deassert"),

      .SYNC_DEPTH              (2)

   ) u_rx_link_rst_sync (

      .reset_in0  (~(wire_link_rst_n & &wire_rx_ready)), 

      .clk        (link_clk),                                

      .reset_out  (rx_link_rst_n_sync)

   );

 

----------------------------------------

 

(2) In module control_unit (control_unit.sv), change the reset value for frame_rst, link_rst, avs_rst & xcvr_rst.

 

----------------------------------------

   //   

   // Output register for base core + transceiver resets   

   // 

   always @ (posedge clk or negedge rst_n)

   begin

      if (~rst_n) begin

         frame_rst <= 1'b1;

         link_rst <= 1'b1;

         avs_rst <= 1'b1;

         xcvr_rst <= 1'b1;

      end else begin

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There is no planned fix for this issue.