Device Family: Intel® Stratix® 10

Type: Errata

Area: Intellectual Property

Last Modified: August 21, 2018
Version Found: v18.0
Version Fixed: v18.1
Bug ID: FB: 587858;

Why do I get warning message (19238) and error message (19192) in FPGA configuration with Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP example design ?


Due to a problem with the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP example design targetting the Intel® Stratix® 10 TX Signal Integrity Development Kit, FPGA configuration will fail with following warning and error message.

Warning message (19238): "Incomplete power management settings for a VID device"

error message (19192): " Power management settings are not set up appropriately on VID part"



To work around this problem, add the required SmartVID Quartus Settings File(.qsf) assignments into the <example design>/hardware_test_design/alt_ehipc3.qsf file to avoid FPGA configuration failure

set_global_assignment -name USE_PWRMGT_SCL SDM_IO14

set_global_assignment -name USE_PWRMGT_SDA SDM_IO11

set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"

set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"

set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER

set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47

set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 48

set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00

set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON




This problem has been fixed starting in the Intel® Quartus® Prime Pro software version 18.1.