Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers, Errata

Area: Intellectual Property


Last Modified: October 16, 2018
Version Found: v18.1
Bug ID: FB: 586318, 595076;

Why do I get fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP, where PTP and RSFEC options have been enabled?

Description

You may see Intel® Quartus® Prime fitter errors when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP when PTP and RSFEC options have been enabled.

This problem is due to incorrect Quartus fitter rules pertaining to channel placement checks when RSFEC and PTP are being used. The checks incorrectly restricted the odd RSFEC locations RSFEC_1 and RSFEC_4 which correspond to the PTP PLL locations.

For further information please refer to the E-Tile Channel Placement Tool.

Workaround/Fix

As a work around, please install the patch below for Intel Quartus Prime v18.1.

quartus-18.1-0.05-windows.exe

quartus-18.1-0.05-linux.run

quartus-18.1-0.05-readme.txt

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.