Device Family: Intel® Stratix® 10 TX

Type: Errata

Area: Intellectual Property


Last Modified: August 14, 2018
Version Found: v18.0 Update 1
Bug ID: FB: 569078;

Why do I get "min_pulse_width" timing violations on my 1588/PTP 10/25G E-tile Hard IP for Ethernet Intel® FPGA IP core?

Description

Due to a problem in the Intel® Quartus® Prime software version 18.0.1, you might see "min_pulse_width" timing violations in the 10/25G 1588/PTP E-tile Hard IP for Ethernet Intel® FPGA IP core. 

Workaround/Fix

There is no workaround for this issue.

This issue is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.