Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property

Last Modified: February 09, 2018

Version Found: v17.1

Bug ID: FB: 527626;

IP: Avalon-ST Stratix 10 Hard IP for PCI Express, Avalon-MM Stratix 10 Hard IP for PCI Express

Why do directed speed changes fail when my Intel® Stratix® 10 PCIe* IP requests a speed change from Gen 3?

Description

Due to a problem with the Intel® Stratix® 10 PCIe* Hard IP, it may fail to send an Electrical Idle Ordered Set (EIOS) when performing a directed speed change out of Gen3 if both of the following requirements are met:

A directed speed change out of Gen3 is requested, and
The far end TX has entered Electrical Idle before the Intel® Stratix® 10 PCIe* Hard IP

This problem does not affect initial link up.

This problem affects all Intel® Stratix® 10 GX L-Tile devices (ES1, ES2, ES3 and Production), all Intel® Stratix® 10 SX L-Tile devices (ES1 and Production), and Intel® Stratix® 10 GX H-Tile ES devices (ES1, ES2). Intel® Stratix® 10 GX H-Tile Production devices are not affected.

Workaround/Fix

To perform the speed change, first down train to Gen1 speed, followed by a retrain to the desired speed. For example, to change from Gen3 to Gen2, first perform a speed change from Gen3 to Gen1, then perform a speed change from Gen1 to Gen2.

This problem is schedule to be fixed in a future Intel® Quartus® Prime software release.

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