In order to read from the transceiver reconfiguration bus of the Intel® Stratix® 10 Low Latency 100Gbps Ethernet Intel® FPGA IP core in simulation, check the "Enable ADME" dialog box in the IP core GUI.
Device Family: Intel® Stratix® 10
Area: Intellectual Property
Last Modified: August 09, 2018
Version Found: v17.1
Bug ID: FB: 579853;