Why can't I read from the transceiver reconfiguration bus of my Intel® Stratix® 10 Low Latency 100Gbps Ethernet IP core in simulation?

In order to read from the transceiver reconfiguration bus of the Intel® Stratix® 10 Low Latency 100Gbps Ethernet Intel® FPGA IP core in simulation, check the "Enable ADME" dialog box in the IP core GUI.