Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: August 09, 2018
Version Found: v17.1
Bug ID: FB: 579853;

Why can't I read from the transceiver reconfiguration bus of my Intel® Stratix® 10 Low Latency 100Gbps Ethernet IP core in simulation?

Description

In order to read from the transceiver reconfiguration bus of the Intel® Stratix® 10 Low Latency 100Gbps Ethernet Intel® FPGA IP core in simulation, check the "Enable ADME" dialog box in the IP core GUI. 

Workaround/Fix

There is no workaround for this issue.