Device Family: Intel® Stratix® 10, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX

Type: Answers

Area: Intellectual Property


Last Modified: October 23, 2018
Version Found: v18.1
Bug ID: FB: 605315;

Why am I writing and reading back incorrect values when accessing the transceiver PMA & PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet Design Example?

Description

Due to a problem in the Intel® Quartus® Prime software version 18.1, writes to the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet Design Example will not take effect. In addition, reads from the transceiver PMA and PCS registers within the Intel Stratix 10 Low Latency 40G Ethernet Design Example will return incorrect values.  

Workaround/Fix

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.