When the E-tile Hard IP for Ethernet Intel® FPGA IP RX MAC receives frame size >= 65536, and enforce_max_frame_size is enabled, the frame output from RX MAC to user logic will be truncated to the frame size specified by max_rx_frame_size setting. A second invalid frame will output from RX MAC to user logic starting from byte-65536 to end of the super large frame.
Device Family: Intel® Stratix® 10, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX
Type: Answers, Errata
Area: Intellectual Property
Last Modified: September 12, 2018
Version Found: v18.0
Bug ID: FB: 594222;
When using the Intel® Stratix® 10, E-tile Hard IP for Ethernet Intel® FPGA IP, oversized frame stripping can cause invalid frames to be presented to user logic.
Description
Workaround/Fix
No workaround or fix is available for this errata problem.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.