Due to a problem with the Intel® Quartus® Prime software version 18.0 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP's avalon_st_rx_pfc_pause_data signal is de-asserted for only one clock cycle after receiving an XON request in PFC implementations. The avalon_st_rx_pfc_pause_data signal continues to be asserted until the pause quanta expire or become zero.
Device Family: Intel® Arria® 10, Intel® Cyclone® 10, Intel® Stratix® 10
Type: Answers, Errata
Area: Intellectual Property
Last Modified: December 17, 2018
Version Found: v17.0
Version Fixed: v18.1
Bug ID: FB: 590118;