Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Errata

Area: HSIO, Intellectual Property

Last Modified: October 10, 2018
Version Found: v18.1
Bug ID: FB: 586318, 595076;
IP: 25G Ethernet, Low Latency 100G Ethernet

Warning (16817): Verilog HDL waring at alt_etipc3_nphy_elane.v (12698)


You may see the warning shown above due to module collision when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP.

When multiple instances of the E-tile Hard IP for Ethernet Intel FPGA IP are used with different configurations within the same Intel® Quartus® Prime project, the design can compile incorrectly which can also cause fitter errors.

Users will see compilation warnings where settings for modules with the same name are overwritten in both Intel Quartus Prime compilation and during simulation compilation.


This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.