Device Family: Intel® Arria® 10

Type: Answers, How-To

Area: Intellectual Property


Last Modified: March 04, 2019
Bug ID: FB: 1506794959;

How can the register values for the Intel® Arria® 10 PCI Express* IP be read or written to?

Description

Reading or writing  Intel® Arria® 10 PCI Express* IP register values is an effective debugging method. Follow the steps below to read or write register values in the Intel® Arria® 10 PCI Express IP components.  First part shows how to enable the Altera Debug Master Endpoint (ADME) in the Arria 10 Transceiver Native PHY IP channels, Intel Arria 10 Transceiver ATX PLL IP Core and Intel Arria 10 Transceiver fPLL IP Core. Second part shows operations on how to read & write register values with Intel® Quartus® Prime Pro Edition System Console.

 

Enabling the ADME feature.

// Arria 10 Transceiver Native PHY IP

1. Enable ADME in the PCI Express IP Parameter Editor (Configuration, Debug and Extension Options tab)

2. Generate HDL   (In Intel Quartus Prime Pro Edition Platform Designer, click "Generate --> Generate HDL ...")

 

// Arria 10 ATX PLL IP Core (Only for Arria 10 PCI Express IP Gen3 mode)

3. Navigate to the directory that includes Platform Designer generated PCI Express design files (e.g. \altera_pcie_a10_hip_171\synth)

4. Open 'lcpll_g3xn.v' file in a text editor

5. Set the following parameters below in ATX/LC PLL instantiation (altera_xcvr_atx_pll_a10)  

.rcfg_jtag_enable                               (1),  

.dbg_embedded_debug_enable    (1),  

.dbg_capability_reg_enable            (1),  

.dbg_stat_soft_logic_enable           (1),  

.dbg_ctrl_soft_logic_enable            (1),

6. Wire up the reconfig clock and reset for the same instantiation   

.reconfig_clk1           (reconfig_clk0),  

.reconfig_reset1         (reconfig_reset0),

7. Save and close 'lcpll_g3xn.v' file

 

// Arria 10 fPLL IP Core

8. Open 'fpll_g3.v' file in a text editor

9. Set the following parameters in fPLL instatiation (altera_xcvr_fpll_a10)  

.rcfg_jtag_enable                              (1),  

.dbg_embedded_debug_enable   (1),  

.dbg_capability_reg_enable           (1),  

.dbg_stat_soft_logic_enable          (1),  

.dbg_ctrl_soft_logic_enable           (1),

10. Wire up reconfig clock and reset for the same instantiation   

.reconfig_clk1             (reconfig_clk0),  

.reconfig_reset1         (reconfig_reset0),

11. Save and close the 'fpll_g3.v' file

12. Start Quartus compilation

13. Download the SOF

 

Register read & write operation with System Console.

1. Start Quartus Transceiver Toolkit and Load Design

2. Check the connected slaves  

% get_service_paths slave     (this list all slaves including XCVR, ATX PLL, and fPLL)

3. Verify the IP information for each slave index and make note of the IP associated with the index  

% marker_get_info [lindex [get_service_paths slave] 0]  

% marker_get_info [lindex [get_service_paths slave] 1]  

% marker_get_info [lindex [get_service_paths slave] 2]  

% marker_get_info [lindex [get_service_paths slave] 3]

4. Reading from/Writing to the XCVR or PLL registers. When writing, do read-modify-write.  (e.g. ATX PLL m_counter)  

% set s [lindex [get_service_paths slave] 3]                                    # index 3 is ATX PLL  

% open_service slave $s  

% set base_addr 0x0000                                                                     # used for accessing transceiver channels   

% set ret [master_read_8 $s [expr $base_addr+0x109*4] 1]     # read ATX PLL address 0x109 (m_counter)  

% set ret [expr $ret & ~0xf0 | (0x1 <<7)]                                         # clear bit[7:4] and set bit[7] to 1  

% master_write_8 $s [expr $base_addr+0x109*4] $ret              # write modified value  

% set ret [master_read_8 $s [expr $base_addr+0x109*4] 1]    # verify by reading back

 

Please refer to Intel Arria 10 Transceiver Register Map for the complete register addresses and values. 

 

 

 

Workaround/Fix