When using the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core with more than one Physical Function enabled, the pool of tags for non-posted requests is shared across all the enabled Physical Functions.
Device Family: Intel® Arria® 10 GX
Area: Intellectual Property
Last Modified: December 12, 2018
Version Found: v18.1
IP: Arria 10 Hard IP for PCI Express