Device Family: Intel® Arria® 10 GX

Type: Answers

Area: Intellectual Property


Last Modified: December 12, 2018
Version Found: v18.1

How do non-posted tag requests work in the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core when more than one Physical Function is enabled?

Description

When using the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core with more than one Physical Function enabled, the pool of tags for non-posted requests is shared across all the enabled Physical Functions.

Workaround/Fix

This additional information is scheduled to be added in a future update to the user guide.