Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10 GX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Intel® Stratix® 10, Stratix® V

Intel Software: Quartus II, Quartus Prime, Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: September 06, 2018
Version Found: v14.0
Bug ID: FB: 543356;
IP: JESD204B

How do I enable polarity inversion on a per lane basis in the JESD204B Intel® FPGA IP?

Description

When using the Avalon®-MM register interface in the JESD204B Intel® FPGA IP, you can enable polarity inversion through bit[0] of lane_ctrl_<n> registers (0x4 - 0x20), where <n> represents the targeted lane number.

Refer to the following links for JESD204B address map and register definitions:

TX: https://www.intel.com/content/www/us/en/programmable/support/literature/ug/altera_jesd204_tx_regmap.html

RX: https://www.intel.com/content/www/us/en/programmable/support/literature/ug/altera_jesd204_rx_regmap.html

For designs that do not use the register interface, follow the instructions in the workaround below, to enable polarity inversion on a per lane basis in the JESD204B Intel® FPGA IP.

Workaround/Fix

If the JESD204B Intel® FPGA IP core register access is unavailable, follow the workaround sequence below to turn on polarity inversion.

Change directory into <IP core name>/altera_jesd204_phy_<acds_version>/<sim or synth>/

Open the file <IP core name>_altera_jesd204_phy_<acds_version>_<random_string>.v with any text editor.

Look for port .csr_lane_polarity in the inst_<tx and/or rx>_mlpcs instantiation.

The width of the input port csr_lane_polarity is L, where L represents the total number of lanes in the JESD204B Intel® FPGA IP core. The LSB represents lane 0, the least significant + 1 bit represents lane 1,..., MSB represents lane L-1.  

To enable polarity inversion, drive 1 to the targeted bit in csr_lane_polarity input port.

 

The following example shows an 8 lanes design, with polarity inverted for lane 0 to lane 2:

module <name>_altera_jesd204_phy_<acds_version>_<random_string> #(

...

altera_jesd204_tx_mlpcs #(

...

) inst_tx_mlpcs (

...

   .csr_lane_polarity         (7'b0000_0111), // TX: polarity inverted for lanes 0-2 

...

);

altera_jesd204_rx_mlpcs #(

...

) inst_rx_mlpcs (

...

   .csr_lane_polarity          (7'b0000_0111), // RX: polarity inverted for lanes 0-2 

... 

);

...