Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers, Errata

Area: Intellectual Property


Version Found: v18.1
Bug ID: FB: 598421;

How do I determine a loss of alignment when using the Intel® Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP in 100G mode with PCS+(528,514)RSFEC or PCS+(544,514)RSFEC IP?

Description

Currently there is no exposed port on the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP when in 100G mode with either PCS+(528,514)RSFEC or PCS+(544,514)RSFEC IP that indicates a loss of alignment.

Workaround/Fix

This will be fixed in a future release of the Intel® Quartus® Prime software.