Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: October 19, 2018
Version Found: v18.1
Bug ID: FB: 604563;
IP: SerialLite III Streaming

How do I access the Transceiver PHY register space using the phy_mgmt_addr port of the Serial Lite III Streaming Intel® FPGA IP Core for Intel® Stratix® 10 L-/H-Tiles?

Description

To access the Transceiver PHY register space using the phy_mgmt_addr port of the Serial Lite III Streaming Intel® FPGA IP Core  for Intel® Stratix® 10 L-/H-Tiles, use the MSB of the bus as follows:

  •     Set phy_mgmt_addr[msb] = 1 to access the Intel Stratix 10 L-/H-Tile Transceiver PHY register space
  •     Set phy_mgmt_addr[msb] = 0 to access the  Serial Lite III Streaming Intel FPGA IP Core Configuration and Status Registers (CSR)

Workaround/Fix

This address usage will be documented in a future revision of the Serial Lite III Streaming Intel FPGA IP Core User Guide.