When an Intel® Arria® 10 FPGA Root Port issues a Hot Reset at Gen3 speed, correctable errors are triggered which is not in complaince with the PCI* Express* specification.
After a Hot Reset is sent from the Intel Arria 10 Root Port to an Endpoint, the Endpoint will reset its credit counterand report its available credit back to the Intel Arria 10 Root Port. The Intel Arria 10 Root Port also needs to reset its credit counter module to ensure synchronization with the Endpoint.
Intel Arria 10 Root Ports have no reset mechanism to reset the credit counter. After Hot Reset event, Intel Arria 10 Root Port's maintained credit counter looses synchronization with the Endpoint, which causes no TLPs to be sent from the Root Port to the Endpoint.