Due to a problem with the LDPC Intel® FPGA IP in Intel® Quartus® Prime Pro software version 17.1 targetting Intel® Stratix® 10, you may observe the above error when compiling the simulation design example generated by the IP configured with WiMedia 1.5 standard and encoder mode in Modelsim.
Device Family: Intel® Stratix® 10
Area: DSP, Intellectual Property
Last Modified: March 08, 2018
Version Found: v17.1
Bug ID: FB: 541664;
IP: DSP, LDPC