Device Family: Intel® Arria® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: June 13, 2018
Version Found: v17.1
Bug ID: FB: 326165;

When using the Intel® Arria® 10 PCIE* IP core, does assertion of a correctable error during speed change from Gen3 x1/x2 to Gen1 or Gen2 mean the link is unreliable?

Description

You may observe a correctable error assertion during the Recovery state when the Intel® Arria® 10 PCIE* IP core changes the speed from Gen3 x1/x2 to Gen1 or Gen2. The corretable error during the speed change does not indicate low link quality and can be ignored. 

Workaround/Fix

No workaround or fix is required for this problem. Once the error is cleared by system software, it should remain deasserted.