You may observe a correctable error assertion during the Recovery state when the Intel® Arria® 10 PCIE* IP core changes the speed from Gen3 x1/x2 to Gen1 or Gen2. The corretable error during the speed change does not indicate low link quality and can be ignored.
Device Family: Intel® Arria® 10
Type: Answers, Errata
Area: Intellectual Property
Last Modified: June 13, 2018
Version Found: v17.1
Bug ID: FB: 326165;
IP: Arria 10 Hard IP for PCI Express