Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Intel® Cyclone® 10

Type: Answers, Errata

Area: HSIO, Intellectual Property

Last Modified: January 29, 2018
Version Found: v16.1 Update 2
Version Fixed: v17.1 Update 1
IP: Arria 10 Hard IP for PCI Express

Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly?


Due to a problem with the Intel® Quartus® Prime version 17.1 and earlier transceiver calibration code, Intel Arria® 10 and Intel Cyclone® 10 PCIe* PIPE PHYs configured for Gen1 and Gen2 configurations may fail to link train correctly and reach the L0 state.


This problem has been fixed starting in Intel Quartus Prime v17.1.1.