Device Family: Intel® Stratix® 10, Intel® Stratix® 10 GX, Intel® Stratix® 10 SX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property

Last Modified: September 25, 2018
Version Found: v18.1
Bug ID: FB: 596245;
IP: Low Latency 100G Ethernet

Why does the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP show 'H-Tile' as 'Target transceiver tile' when targeting a 'L-Tile' only device?


When working with a 'L-Tile' only device, the 'Target transceiver tile' drop down menu is disabled and shows the 'H-Tile' default value. 'H-Tile' is coded in the component description file as its default.


The designer can safely ignore the 'H-Tile' as 'Target transceiver tile' when targetting L-Tile devices, the IP will generate HDL targeting the correct device tile. This problem will be fixed in a future release of the Intel® Quartus® Prime software.