Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: October 30, 2018
Version Found: v18.1
Bug ID: FB: 589925;

Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?

Description

Due to a problem in the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1, you may observe a minimum pulse width timing violation information message during compilation.

Workaround/Fix

This message can be safely ignored.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.