Due to a problem with the write address decoding for the Intel® Arria® 10 PCI Express* Hard IP, you may fail to clear the lane error status register after writing ‘1’ to this register.
Device Family: Intel® Arria® 10
Type: Answers, Errata
Area: Intellectual Property
Last Modified: October 29, 2018
Version Found: v17.1
Bug ID: FB: 588930;
IP: Arria 10 Hard IP for PCI Express