Device Family: Intel® Arria® 10 GX, Intel® Cyclone® 10 GX

Type: Answers

Area: Intellectual Property


Last Modified: November 22, 2018
Version Found: v18.0
Version Fixed: v18.1
Bug ID: FB: 568796;

Why does the 'Size' parameter for the BAR0 to BAR5 is set to 4 by default in the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* version 18.0?

Description

Due to a problem in the Intel® Arria® or Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* version 18.0, the 'Size' parameter for BAR0 to BAR5 is read only and set to 4 by default.

Workaround/Fix

To work around this problem, migrate your design to the Intel® Arria® or Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* version 18.1.