You may see Transmission Error when running a single lane SerialLite III IP core implementation on Stratix® 10 on hardware if Required idle cycles between bursts parameter value is set to 2.
Device Family: Intel® Stratix® 10, Intel® Stratix® 10 GX, Intel® Stratix® 10 SX
Area: Intellectual Property
To work around this problem, change Required idle cycles between bursts value to 1. Regenerate and Recompile.
This problem is scheduled to be fixed in the next full production release of the Quartus® II Prime Pro software.