Device Family: Intel® Stratix® 10, Intel® Stratix® 10 GX, Intel® Stratix® 10 SX

Type: Answers

Area: Intellectual Property


Last Modified: June 16, 2017
Version Found: v17.0
Bug ID: FB: 468760;
IP: SerialLite III Streaming

Why might I see transmission errors when running a single lane SerialLite III IP core implementation on Stratix 10 hardware?

Description

You may see Transmission Error when running a single lane SerialLite III IP core implementation on Stratix® 10 on hardware if Required idle cycles between bursts parameter value is set to 2.

Workaround/Fix

To work around this problem, change Required idle cycles between bursts value to 1. Regenerate and Recompile.

This problem is scheduled to be fixed in the next full production release of the Quartus® II Prime Pro software.