Device Family: Intel® Arria® 10 GX, Arria® V, Intel® Stratix® 10, Stratix® V

Type: Answers

Area: Intellectual Property


Last Modified: July 24, 2017
Version Found: v16.1
Version Fixed: v17.0
Bug ID: FB: 414238;

Why Low Latency Ethernet 10G MAC 10M/100M/1G/10G Example Design may fail timing on multiple channels?

Description

The following variants of Intel® Low Latency Ethernet 10G MAC example design may fail timing when number of channel more than or equal to 7.
 1. 10M/100M/1G/10G Ethernet
 2. 10M/100M/1G/10G Ethernet with 1588
 3. 1G/10G Ethernet
 4. 1G/10G Ethernet with 1588

Workaround/Fix

This issue has been fixed in Quartus® Prime software versions 17.0 and onwards.