Description
The DisplayPort Intel® FPGA IP Sink may assert CR_Lock due to receiver noise. The invalid CR_Lock may result in an incorrect IRQ_HPD assertion before the video source initiates link training.
DisplayPort Intel® FPGA IP Source devices should ignore this incorrect IRQ_HPD assertion until link training begins.
Resolution
This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 17.1.