Article ID: 000075684 Content Type: Troubleshooting Last Reviewed: 01/09/2023

Why does IRQ_HPD of the DisplayPort Intel® FPGA IP unexpectedly assert before a video source initiates link training?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The DisplayPort Intel® FPGA IP Sink may assert CR_Lock due to receiver noise. The invalid CR_Lock may result in an incorrect IRQ_HPD assertion before the video source initiates link training.

    DisplayPort Intel® FPGA IP Source devices should ignore this incorrect IRQ_HPD assertion until link training begins.

     

    Resolution

    This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 17.1.

    Related Products

    This article applies to 4 products

    Arria® V FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Stratix® V FPGAs