Article ID: 000075615 Content Type: Troubleshooting Last Reviewed: 01/31/2023

Why is there no video output from my Video IP core when run time control is enabled?

Environment

  • Video and Image Processing
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You will see this behavior on any of the Video IP cores (e.g. Scaler II, Color Space Converter, etc.) if you have any run-time control enabled but do not assert the Go bit in the Control Register.

    The Go bit of all the Video IP cores is asserted by default if there is no run-time control enabled, or if they do not have a run time control option. However, if any run time control option is enabled, the Go bit for that core will be de-asserted by default. 

     

    Resolution

    To work around this problem, remember to assert the Go bit in the Control register if you have enabled any run time control for a Video IP core.

    This is clarified in the Video IP User Guide version 2017.11.06.

    Related Products

    This article applies to 9 products

    Arria® II FPGAs
    Arria® V FPGAs and SoC FPGAs
    Cyclone® IV FPGAs
    Intel® MAX® 10 FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Stratix® IV FPGAs
    Stratix® V FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs

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