Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: November 27, 2017
Version Found: v17.1
Bug ID: FB: 492436;

Why is the waitrequest signal not asserted during reset when simulating my Stratix 10 40 Gbps Ethernet IP core?

Description

Due to a problem in the Intel® Quartus® Prime software release 17.1, in simulation you will see the waitrequest signal stay deasserted (low) even while reset is asserted.  This is a violation of the Avalon®-MM specification and may result in errors from some testbenches, but is not a functional issue.

Workaround/Fix

To work around this problem, you can ignore this behavior, and either ignore the testbench errors or downgrade them to warnings.

This problem is scheduled to be fixed in a future Quartus Prime software release.