Device Family: Cyclone® V

Type: Answers

Area: Intellectual Property

Last Modified: June 19, 2017
Version Found: v16.0
Bug ID: FB: 477789;
IP: Cyclone V Hard IP for PCI Express, Avalon-MM Cyclone V Hard IP for PCI Express

Why is app_int_ack status signal not available for PCI Express Hard IP Core of Cyclone V devices?


This status signal is not offered for Cyclone® V devices 


To work around this issue, please refer to app_msi_ack status signal to indicate completion of app_int_sts_vec signal assertion and deassertion