Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10, Stratix® V

Type: Answers, Errata

Area: Intellectual Property

Last Modified: December 05, 2017
Version Found: v15.0
Version Fixed: v16.1 Update 1
Bug ID: FB: 412054;

Why are the Intel® FPGA HDMI IP Core Trailing Scrambled Data Island Guardbands For Channel 1 & 2 Not Encoded Correctly?


When using the Intel® FPGA HDMI IP core for HDMI TX 2.0 operation, errors will be observed for channel 1 and 2 if the attached HDMI sink implements character error detection.

This is due to the data island trailing guardbands for channel 1 and 2 not being TMDS encoded correctly.

The Intel FPGA HDMI IP Core TX module does not ensure "cnt" track data stream disparity during the data island periods,  which violates the HDMI 2.0 specification. This problem should have no impact to the video display.


There is no workaround for this problem.
This problem is fixed in Intel® Quartus® version 16.1 update 1 of the Intel FPGA HDMI IP core.