Article ID: 000075397 Content Type: Troubleshooting Last Reviewed: 12/05/2017

Why are the Intel® FPGA HDMI IP Core Trailing Scrambled Data Island Guardbands For Channel 1 & 2 Not Encoded Correctly?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When using the Intel® FPGA HDMI IP core for HDMI TX 2.0 operation, errors will be observed for channel 1 and 2 if the attached HDMI sink implements character error detection.

    This is due to the data island trailing guardbands for channel 1 and 2 not being TMDS encoded correctly.

    The Intel FPGA HDMI IP Core TX module does not ensure "cnt" track data stream disparity during the data island periods,  which violates the HDMI 2.0 specification. This problem should have no impact to the video display.

    Resolution

    There is no workaround for this problem.
    This problem is fixed in Intel® Quartus® version 16.1 update 1 of the Intel FPGA HDMI IP core.

    Related Products

    This article applies to 4 products

    Intel® Cyclone® 10 FPGAs
    Stratix® V FPGAs
    Arria® V FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs