Device Family: Intel® Arria® 10, Arria® V GT, Arria® V GX, Arria® V GZ, Arria® V ST, Arria® V SX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Intel® Stratix® 10, Stratix® V

Type: Errata

Area: Intellectual Property

Last Modified: April 06, 2017
Version Found: v16.0
Version Fixed: v17.0
Bug ID: FB: 389461;
IP: RapidIO II (IDLE2 up to 6.25 Gbaud)

Why does the RapidIO II IP Core transmit when TX digital reset is asserted?


Due to a bug in the RapidIO II IP Core, the transceiver can start transmitting 0xBC characters before TX Digital Reset (tx_digitalreset on Arria® 10, or tx_digitalreset_stat on Stratix® 10) has been de-asserted.

This can cause some link partners to incorrectly detect IDLE1 sequence. The detection of IDLE1 sequence is a defined implementation.

Note that RapidIO II IP Core uses IDLE2 sequence.



This problem has been fixed starting in software version 17.0 of the RapidIO II IP core.