Device Family: Intel® Arria® 10, Arria® V GT, Arria® V GX, Arria® V GZ, Cyclone® V, Intel® Stratix® 10, Stratix® V

Type: Errata

Area: Intellectual Property

Last Modified: April 05, 2017
Version Found: v15.0
Version Fixed: v17.0
Bug ID: FB: 439527;
IP: RapidIO II (IDLE2 up to 6.25 Gbaud)

Why does the RapidIO II auto-generated VHDL simulation testbench fail to compile in certain configurations of the RapidIO II IP core?


In some configurations of the RapidIO® II IP core, generated VHDL simulation will encounter compilation error where a port is missing in the entity instantiating another entity.
Example Error in ModelSim® simulator.

Port "<port_name>" of entity "<entity name>" is not in the component being instantiated.

​This error is only found in variations where the I/O Master, I/O Slave, Doorbell, Maintenance or Pass-through modules are disabled.

Verilog version is not impacted.


Use Verilog version of the simulation testbench.