Due to a problem with Intel® Quartus® Prime version 17.1, the Low Latency Ethernet 10G MAC's dynamically generated multi-rate example design will fail compilation if the "Analog Voltage" setting is changed to 1_1V in Low Latency Ethernet 10G MAC example design GUI.
The following are the affected multi-rate example design variants:
- 10G USXGMII Ethernet Example Design (Intel® Stratix® 10)
- 10M/100M/1G/2.5G/10G Ethernet Example Design (Stratix 10)
- 1G/2.5G Ethernet with 1588 Example Design (Stratix 10)
- 1G/2.5G/10G Ethernet with 1588 Example Design (Stratix 10)