Why does the Low Latency 40G IP Core fail timing closure when operating in KR4 mode on Arria 10?

Device Family: Intel® Arria® 10, Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers, Errata

Area: Intellectual Property

Description

Due to a problem with the Low Latency 40G MAC IP Core operating in KR4 mode on Intel® Arria® 10 Devices, Timing closure setup failure may be seen due to clocks incorrectly promoted to "Regional" instead of "Periphery" network.

Workaround/Fix

To work around this problem, add the follow assignments to your projects Quartus® Settings File(.qsf). These additional assignments will force the failing *out_pld_pcs_tx_clk_out and *out_pld_pcs_rx_clk_out clocks on to the periphery network. Note that an assignment is required for each lane.

set_instance_assignment -name GLOBAL_SIGNAL PERIPHERY_CLOCK -to *e40_inst*g_xcvr_native_insts[*]*twentynm_xcvr_native_inst*inst_twentynm_pcs*_pld_pcs_tx_clk_out
set_instance_assignment -name GLOBAL_SIGNAL PERIPHERY_CLOCK -to *e40_inst*g_xcvr_native_insts[*]*twentynm_xcvr_native_inst*inst_twentynm_pcs*_pld_pcs_rx_clk_out

This problem is scheduled to be fixed in a future release of the Quartus Prime software.