Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10 GX, Cyclone® V GT, Cyclone® V GX, Cyclone® V SX, Intel® Stratix® 10, Stratix® V GS, Stratix® V GT, Stratix® V GX

Type: Answers

Area: Intellectual Property

Last Modified: May 24, 2019
Version Found: v14.0
Bug ID: 1507183483

Why does the JESD204B IP flag an incorrect Lane Deskew Error after re-initialization?


Due to a problem in the Intel® Quartus® Prime and Prime Pro software versions 17.1.1 or earlier, the JESD204B IP generated for Intel Cyclone® V, Arria® V, Stratix® V, Cyclone 10 GX, Arria 10 or Stratix 10 devices might flag an incorrect Lane Deskew Error (bit-4 of RX Error Status 0) after re-initialization, because different lanes have lost their alignment at different times, which results in a false error. 


To work around this, follow the steps below to clear the csr_lane_deskew_err interrupt bits after re-initialization. 

1. Always disable the rx_err_reinit_en bit for deskew error to avoid infinite re-initialization due to deskew error.

2. Ignore the deskew error that occurs after re-initialization, as it is falsely flagged.

3. Follow the steps in section “Programmable RBD Offset” in the JESD204B Intel FPGA IP User Guide to clear the real deskew error that happens after reset (not the deskew error after re-initialization). 

There are no plans to fix this problem in the JESD204B Intel FPGA IP.