In the JESD204B example design targetting Arria® 10 or Stratix® 10 devices, the ATX PLL component shares the same reference clock frequency with the CDR clock frequency. For duplex mode (Data path: Duplex), you can select a valid reference clock from the PLL/CDR Reference Clock Frequency drop down menu in the IP parameter editor. For simplex TX mode (Data path: Transmitter), the drop down menu is not available for selection and the example design generation will take the previous valid reference clock frequency from the drop down. This may cause an error during example design generation.
To avoid this error for simplex TX example design generation, follow the sequence below when configuring the JESD204B IP parameters:
Enter the desired Data rate.
Choose a valid reference clock from PLL/CDR Reference Clock Frequency drop down**.
Select Data path: Transmitter
Configure the rest of the parameters.
**Refer to the Arria 10/Stratix 10 Device Datasheet for a valid range of reference clock frequency for the ATX PLL.
This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro software