Device Family: Intel® Arria® 10

Type: Answers, Errata

Area: Intellectual Property

Last Modified: November 02, 2017
Version Found: v15.1
Bug ID: FB: 318367;

Why does the "Generate Example Design" button not work when the 10G Low Latency MAC core is launched from Qsys IP Catalog?


Due to a problem in the Quartus® Prime software, when 10G Low Latency MAC core is added to a Qsys(Platform Designer) system from the Qsys IP Catalog, activating the "Generate Example Design" button in the IP parameter editor may cause the following Qsys error message to appear:

"The example design cannot be generated when there are errors."

The errors mentioned are system-level connectivity errors which are shown in the Qsys "messages" window. 


To work around this issue, generate the example design by invoking the 10G Low Latency MAC core IP parameter editor from the standalone Quartus IP Catalog not from within Qsys(Platform Designer).

This problem is scheduled to be fixed in a future release of the Quartus Prime software.