When the Intel® Arria® 10 PCIe* Hard IP core receives TS2 training sequences during the Polling.Config state, automatic lane polarity inversion is not guaranteed. The link may train to a smaller than expected link width or may not train successfully. For example, a PCIe x8 link may train to x4. This can affect configurations with any PCIe speed and width.
Automatic lane polarity inversion is supported when the Arria 10 PCIe Hard IP receives TS1 training sequences during the Polling.Active state.