Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property

Last Modified: October 09, 2017
Version Found: v17.0 Update 1
Version Fixed: v17.1
Bug ID: FB: 492659;
IP: Interlaken IP Core (2nd Generation), interlaken

Why does simulation fail when using the Interlaken design example?


Due to a problem in the Interlaken IP Core (2nd Generation), the rx_digitalreset and reset_stat keep toggling when using the modelsim or ncsim simulation environment. As a result, the simulating system can't enter lock status or finish successfully.


This problem does not exist when using the VCS simulation environment.

This problem has been fixed starting in version v17.1 of the Intel® Quartus® Prime software.