Due to a problem with the Intel® Low Latency 40- and 100-Gbps Ethernet IP cores, rx_pcs_ready and bit of the PHY_RXPCS_STATUS register will not assert during link training, if bit of the PHY_SCLR_FRAME_ERROR register (offset 0x324) is set.
Device Family: Intel® Arria® 10, Stratix® V GS, Stratix® V GT, Stratix® V GX
Area: Intellectual Property
Bit of the PHY_SCLR_FRAME_ERROR register should be set only when reading the PHY_FRAME_ERROR register (offset 0x323). It should be de-asserted soon after reading the PHY_FRAME_ERROR register (offset 0x323).
This is not scheduled to be fixed in any future Quartus® Prime software release.